1. Field of the Invention
This invention relates to a semiconductor storage device.
2. Related Background Art
Conventional 1T-1C (one transistor-one capacitor) type DRAM cells are getting more and more difficult to fabricate along with their progressive microminiaturization. As their substitutes, FBC memory cells have been proposed. In FBC memory cells, since a single MIS (Metal Insulator Semiconductor) FET constitutes each unit element for storing one-bit information, the area one cell occupies is small. Therefore, FBC memory cells make it possible to form a larger-capacity storage element in a unit area (see Japanese Patent Laid-open Publications JP-2003-68877, JP-2002-246571 and 2003-31693).
In conventional FBC memory cells, since individual memory cells are positioned at intersections of word lines and bit lines, when a single word line is powered, all bit lines read out data in the memory cells on the powered word line. Therefore, conventional FBC cells cannot help employing an open bit line structure.
Such an open bit line structure has to place sense amplifiers in the same intervals as those of the bit lines. As the line-to-line distance of the bit lines is reduced, it makes the layout of sense amplifiers more difficult. Moreover, since the open bit line configuration requires a large area for sense amplifiers (i.e. the distance between adjacent memory cell arrays), it inevitably results in reducing the share of the area or volume the memory cells can occupy.
Among some open bit line configurations, there is a technique of employing a double end structure for bit lines (see FIG. 7). In the double end structure, it is sufficient to allocate one sense amplifier to every two memory bit lines in a certain memory cell array. Therefore, this technique can improve the share of memory cells to a certain extent. Nevertheless, it has not reached the fundamental solution of the issue of the share of memory cells. Furthermore, the double end structure involves the problem that, in memory cells at opposite ends of a set of arrays comprising a plurality of memory cell arrays, the number of bit lines is reduced to a half the number of bit lines in other memory cell arrays (see FIG. 7). This results in lowering the density of memory cells.
Therefore, a semiconductor storage device having a high share of memory cells by increasing a density of the memory cells and by decreasing an occupied area of sense amplifiers is desired.